As integrated circuits continue to scale downward in size, the finFET (fin field effect transistor) is becoming an attractive device for use with smaller nodes, e.g., the 22 nm node and beyond. In a finFET, the channel is formed by a semiconductor fin and a gate electrode is located on at least two sides of the fin. Due to the advantageous feature of full depletion in a finFET, the increased number of sides on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET compared to a planar MOSFET. The improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. A finFET device generally has faster switching times, equivalent or higher current density, and much improved short channel control than planar CMOS technology utilizing similar critical dimensions.
Two of the main detractors for realizing such finFET device technology are the higher Ceff and ineffectiveness of conventional stress elements such as eSiGe or stress liner. Any innovation in device architecture which can reduce either of these components will help in improving the performance of the finFET device circuits
In order to reduce the high resistance of thin body Si, finFET or trigates are typically merged in the source drain (S/D) area to reduce the external resistance. However, with such device integration, the Ceff of the device is higher since there is a finite gate-to-EPI capacitance as the conductive part of the gate in non-fin areas and the EPI merge is separated by the spacer. Such dead areas in the gate cannot be avoided in finFET or trigates devices.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.